发明名称 |
Successive-approximation analog-digital converter and related operating method |
摘要 |
A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter. The converter includes a device which enables the increase of the first analog signal in output from the digital-analog converter and in input to the comparator by a preset value (Voffs) when the bit of the first digital signal which corresponds in position to the bit of the second digital signal which must be decided in a clock cycle is zero.
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申请公布号 |
US2001038352(A1) |
申请公布日期 |
2001.11.08 |
申请号 |
US20010838090 |
申请日期 |
2001.04.18 |
申请人 |
BARDELLI ROBERTO;TARANTOLA MARIO |
发明人 |
BARDELLI ROBERTO;TARANTOLA MARIO |
分类号 |
H03M1/38;H03M1/08;H03M1/46;(IPC1-7):H03M1/34 |
主分类号 |
H03M1/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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