| 摘要 |
A cache system, used in conjunction with a processor of a computer system, is disclosed herein for increasing the processor access speed. The cache system comprising a cache controller in communication with the processor and cache memory in communication with the cache controller. The cache memory comprising a number of cachelines for storing data, each cacheline having a predefined number of entries. The cache system further comprises a buffer system in communication with the cache controller. The buffer system comprising a number of registers, each register corresponding to one of the entries of a filling cacheline. Each respective register stores the same data that is being filled into the corresponding entry of the filling cacheline. Unlike the data in the filling cacheline, the data in the registers of the buffer system can be accessed during a cacheline filling process.
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