NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations

摘要

Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.

主权项

1. A high-density NAND (HiNAND) flash memory array with 1-level broken-bit-line hierarchical architecture for performing multiple-WL All-BL simultaneous Program, Program-Verify, and Read operations, the HiNAND flash memory array comprising:
a NAND memory array arranged in a first plurality of Groups per N columns respectively associated with N global bit lines (GBLs) parallel to each other cascaded in a row, the N GBLs being respectively divided into the first plurality of broken-GBLs separated/connected from/to each other correspondingly by a row of N Group-divided devices, each Group being further divided into a second plurality of Segments such that the N broken-GBLs associated with the Group are respectively divided into the second plurality of N segmented-GBLs separated/connected from/to each other correspondingly by a row of N Segment-divided devices, each Segment including multiple Blocks, each Block including M Pages of NAND memory cells forming into N Strings, each String having M NAND memory cells connected in series capped by a first String-select device coupled to the corresponding segmented-GBL and a second String-select device coupled to a common source line in parallel to a word line (WL) of each Page; a row of N precharge pull-down devices per Segment with N individual drains and sources respectively coupled between the N segmented-GBLs associated to the Segment and a precharge-power line in parallel to the common source line connected to a voltage decoder for precharging and discharging all the N segmented-GBLs in the Segment selected from any Group independent from other Segments in all Groups; a page buffer having N-bit ports to couple with the N GBLs, the page buffer comprising at least a first Data Register coupled with a first Cache Register located at a first end of the first plurality of columns near a first one of the first plurality of Groups of the array; wherein each row of N Group-divided devices is commonly gated by one of first control signals, each row of N Segment-divided devices is commonly gated by one of second control signals, each row of N precharge pull-down devices per Segment is commonly gated by one of third control signals, multiple Pages across the NAND memory array can be selected on one-page-per-block basis from multiple dispersed Blocks in multiple different Segments of one or more Groups for at least partially performing simultaneous Program, Program-Verify, and Read operations.