| 摘要 |
PROBLEM TO BE SOLVED: To shorten verification scenario generation time while reducing an operator's burden in generation of a verification scenario used for logic verification of an integrated circuit. SOLUTION: The device comprises a verification test bench generation part 12 which generates a verification test bench based on a device list input of which is received by a first input part 10, 10' and parameter setting information; a scenario template generation part 13 which generates a scenario template by describing initial setting information to the test bench; a data combination list generation part 14, 14' which generates a data type combination list related to the verification test bench; a verification item generation part 15 which generates a verification item based on the data type combination list and a combination list of test benches input of which is received by the first input part 10; and a verification scenario generation part 16, 16' which generates a verification scenario based on the scenario template and the verification item. COPYRIGHT: (C)2008,JPO&INPIT
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