GATE-ALL-AROUND VERTICAL GATE MEMORY STRUCTURES AND SEMICONDUCTOR DEVICES, AND METHODS OF FABRICATING GATE-ALL-AROUND VERTICAL GATE MEMORY STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF

摘要

Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around vertical gate semiconductor structure comprising forming a plurality of layers over a substrate, the plurality of layers having alternating first insulative material layers and conductive material layers; identifying bit line and word line locations for the formation of bit lines and word lines; removing portions of the plurality of layers outside of the identified bit line and word line locations; forming vertical second insulative material structures in areas outside of the identified bit line and word line locations; removing portions of the plurality of layers in areas along the identified word line locations outside of the identified bit line locations; removing the first insulative material from the first insulative material layers in areas along the identified word line locations; forming bit lines in the identified bit line locations; and forming word lines in the identified word line locations.

主权项

1. A method of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure, the method comprising:
providing a substrate; forming a plurality of layers over the substrate, the plurality of layers having alternating first insulative material layers and conductive material layers, the first insulative material layers formed by a deposition of first insulative material and the conductive material layers formed by a deposition of conductive material; identifying bit line and word line locations for the formation of bit lines and word lines; removing portions of the plurality of layers outside of the identified bit line and word line locations, each said removed portion extending through the plurality of layers to at least a top surface of the substrate; forming vertical second insulative material structures in areas outside of the identified bit line and word line locations; removing portions of the plurality of layers in areas along the identified word line locations outside of the identified bit line locations, each said removed portion extending through the plurality of layers to at least a top surface of the substrate; remove the first insulative material from the first insulative material layers in areas along the identified word line locations; forming bit lines in the identified bit line locations by:
rounding at least a portion of each of the conductive material layers along the identified bit line locations; andforming a charge storage layer over at least a portion of the rounded conductive material layers; and forming word lines in the identified word line locations.