| 摘要 |
The circuit comprises two identical multiplication cells (C1,C2), each with two inputs (E1,E2) and an output (S), and an addition circuit (ADD), for adding the output signals of two cells in order to obtain an output signal devoid of a direct component. The input sinusoidal signals (S1(t), S2(t)) are applied to the respective inputs of the first cell (C1), and crossed to the inputs of the second cell (C2). The output signal (O1(t),O2(t)) of the two cells are added to give the output signal (O(t)) of the circuit without the direct component. The two multiplication cells (C1,C2) are paired and implemented in the same integrated circuit. Each multiplication cell (C1,C2) contains two phase-delay elements (Phase SIMILAR F1, Phase phi 2), one for each input, and an ideal multiplication circuit. The output signal (O(t)) is sinusoidal, has the frequency doubled, the amplitude equal to the product of two amplitudes, and the direct components cancelled out by addition.
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