| 发明名称 |
METHOD AND APPARATUS FOR MODELING DELAYS IN EMULATION |
| 摘要 |
A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler. |
| 申请公布号 |
US2016292334(A1) |
申请公布日期 |
2016.10.06 |
| 申请号 |
US201514679954 |
申请日期 |
2015.04.06 |
| 申请人 |
Synopsys, Inc. |
发明人 |
RABINOVITCH Alexander;Alquier Cedric;Delerse Sebastien |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A hardware verification system comprising a plurality of programmable devices, said plurality of programmable devices comprising a master scheduler, a plurality of schedulers and a plurality of programmable delay elements, wherein a first one of the plurality of schedulers is configured to:
receive one or more delay values associated with one or more of the plurality of delay elements, wherein each of the plurality of programmable delay elements corresponds to a delay; send a parameter corresponding to the one or more delay values to the master scheduler; and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler. |
| 地址 |
Mountain View CA US |
