发明名称 An apparatus and method for a buffered interconnect
摘要 An interconnect for transferring requests between source and destination ports, includes buffer storage circuitry for the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry. This reduces head of line blocking, where requests for an unengaged port are blocked by a backlog of requests exists, and is less complex than protocols requiring re-transmission. The share buffer allows reordering of requests to allow more efficient use of interconnect bandwidth.
申请公布号 GB2533970(A) 申请公布日期 2016.07.13
申请号 GB20150000428 申请日期 2015.01.12
申请人 ARM Limited 发明人 Andrew David Tune;Sean James Salisbury
分类号 G06F13/40 主分类号 G06F13/40
代理机构 代理人
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