GATE DRIVER CIRCUIT, AND IMAGE DISPLAY APPARATUS INCLUDING THE SAME

摘要

A gate driver IC (i.e., gate driver circuit), when set to a first mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with one clock cycle of a clock inputted to the terminal CLK** (clock input terminal), and outputs a selection voltage or a non-selection voltage based on a data position in the gate driver IC; and when set to a second mode by a logic signal of the tenninal FNC*, shifts data in the gate driver IC in synchronization with n clock cycles (n is an integer of at least 2) of a clock inputted to the terminal CLK**, and outputs the selection voltage or the non-selection voltage based on the data position in the gate driver IC.

主权项

1. A gate driver circuit included in an image display apparatus that includes a display screen in which pixels are disposed in a matrix, the gate driver circuit comprising:
a clock input terminal; a data input terminal; a plurality of output terminals connected to gate signal lines of the image display apparatus; and a setting circuit for setting a first mode or a second mode, wherein a selection voltage or a non-selection voltage output from an arbitrary one of the plurality of output terminals is applied to a corresponding one of the gate signal lines, data set at the data input terminal is provided to the gate driver circuit according to a clock inputted to the clock input terminal, the data is shifted in the gate driver circuit in synchronization with the clock inputted to the clock input terminal, the arbitrary one of the plurality of output terminals outputs the selection voltage or the non-selection voltage based on a data position in the gate driver circuit, when the setting circuit is set to the first mode,
the data is shifted in the gate driver circuit in synchronization with one clock cycle of the clock inputted to the clock input terminal, and the selection voltage or the non-selection voltage is output based on the data position in the gate driver circuit, and when the setting circuit is set to the second mode,
the data is shifted in the gate driver circuit in synchronization with n clock cycles of the clock inputted to the clock input terminal, and the selection voltage or the non-selection voltage is output based on the data position in the gate driver circuit, n being an integer of at least 2.