| 发明名称 |
APPARATUSES AND METHODS TO PREVENT EXECUTION OF A MODIFIED INSTRUCTION |
| 摘要 |
Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation. |
| 申请公布号 |
US2016283234(A1) |
申请公布日期 |
2016.09.29 |
| 申请号 |
US201514672158 |
申请日期 |
2015.03.28 |
| 申请人 |
Intel Corporation |
发明人 |
XEKALAKIS POLYCHRONIS;Collins Jamison D.;Agron Jason M. |
| 分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a hardware binary translator to translate an instruction to a translated instruction; and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation. |
| 地址 |
Santa Clara CA US |
