发明名称 |
DATA PROCESSING METHOD, DATA PROCESSOR, SOLID-STATE IMAGING APPARATUS, IMAGING APPARATUS, AND ELECTRONIC APPLIANCE |
摘要 |
PROBLEM TO BE SOLVED: To perform simultaneous processing of a multiplication/addition operation processing and AD conversion while suppressing an increase in area of a counter circuit in a solid-state imaging apparatus for adopting a reference signal comparison type AD conversion system. SOLUTION: According to a data processing method, when processing a reset level Srst, count processing is performed in an up-count mode from when a reference signal Vslop and the reset level Srst become identical till when a maximal AD conversion period is reached with a negative number of a maximal count number Drm as an initial value Dini. When processing the signal level Ssig, the count processing is performed in the up-count mode from when the reference signal Vslop starts changing from the initial value SLP_ini till when the reference signal Vslop and the signal level Ssig become identical. Count value D2 held in a counter part 254 after the processing of the signal level Ssig indicates data Dsig of a signal element Vsig to be a subtraction processing result between the reset level Srst and the signal level Ssig. COPYRIGHT: (C)2008,JPO&INPIT
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申请公布号 |
JP2008227800(A) |
申请公布日期 |
2008.09.25 |
申请号 |
JP20070061568 |
申请日期 |
2007.03.12 |
申请人 |
SONY CORP |
发明人 |
SUZUKI ATSUSHI;WATANABE TAKANORI |
分类号 |
H04N5/335;H04N5/341;H04N5/369;H04N5/374;H04N5/3745;H04N5/376;H04N5/378 |
主分类号 |
H04N5/335 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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