System and method for executing a plurality of instructions in a processor having a pipeline

摘要

PROBLEM TO BE SOLVED: To obtain a system which executes instructions with a pipeline type processor through generation of a control return address by combining the count value of a counter with a 1st stage number, when a conditioned call instruction satisfies the conditions. SOLUTION: A processor 12 includes a pipeline 22 having pipeline stages. A fetch stage 24 obtains an instruction from a memory position in a program memory 16. A predecoding stage 26 performs operation accompanying preparations of a decoding stage 28 for decoding the instruction. A read stage 30 reads all data, which are needed for executing the instruction to be decoded by the decoding stage 28, out of a data memory 18. The fetch stage 24 calculates an address specifying a memory position in the program memory 16 to receive a next instruction, when the execution of an instruction accompanying the conditioned call instruction is completed. This calculation reduces the silicon area that the processor 12 requires.