发明名称 INTEGRATED CIRCUIT WHICH USES AN ETCH STOP FOR PRODUCING STAGGERED INTERCONNECT LINES
摘要 <p>A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.</p>
申请公布号 EP0912996(B1) 申请公布日期 2002.01.02
申请号 EP19970929752 申请日期 1997.05.27
申请人 ADVANCED MICRO DEVICES, INC. 发明人 BANDYOPADHYAY, BASAB;FULFORD, H., JIM, JR.;DAWSON, ROBERT;HAUSE, FRED, N.;MICHAEL, MARK, W.;BRENNAN, WILLIAM, S.
分类号 H01L21/768;H01L23/522;(IPC1-7):H01L21/768 主分类号 H01L21/768
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