Sampling circuit and sampling method

摘要

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

主权项

1. A sampling circuit for sampling an input voltage and generating an output voltage, comprising:
a switch, switching off in a first switching state and switching on to make the output voltage equal to the input voltage in a second switching state, wherein the switch has a control terminal; a capacitor, coupled to the switch; a first switch group, coupled to the capacitor; a second switch group, coupled to the capacitor; and a voltage buffer, coupled to the switch, the capacitor, the first switch group and the second switch group, having large input impedance, wherein an input of the voltage buffer receives the input voltage and an output of the voltage buffer provides a voltage which is equal or close to the input voltage; wherein, in the first switching state when the first switch group switches on and the second switch group switches off, the capacitor is charged to generate a voltage difference across the two terminals thereof, and in the second switching state when the first switch group switches off and the second switch group switches on, the input voltage is coupled to the control terminal of the switch through the voltage buffer and the capacitor so that a voltage at the control terminal is substantially equal or close to the input voltage plus the voltage difference across the capacitor.