| 摘要 |
<p>The invention relates to a data processing circuit that comprises, in combination: a data processing unit (UB) including two signal-conversion circuits (Inv1, Inv2) each having a signal input and a signal output, and a series of controlled switches (R1, W1, R2, W2) connected to the inputs and outputs of said conversion circuits, said data processing unit further including a binary signal inlet (H) and a binary signal outlet (F), a memory unit (dram) including a series of capacities (Ccell) connected to a memory bus arrangement (bus dRAM) via another series of switches and each capable of storing a binary piece of data, the bus being connected to the processing unit, a set of inputs for the control signals of the controlled switches, the data processing unit (UB) being capable of carrying out at least the following operations in response to data sequences of control signals: writing a binary datum in a capacitor, reading from a capacitor a binary datum stored therein and applying the datum to the output, and logically combining binary data stored in at least two capacitors.</p> |
