发明名称 |
Semiconductor integrated circuit |
摘要 |
According to one embodiment, a semiconductor integrated circuit includes a clock signal transmission path configured to transmit a clock signal and a data transmission path configured to transmit data. The clock signal transmission path has a first and a second clock signal transmission line configured to transmit a clock signal and a complementary clock signal. The data transmission path has a first and a second data transmission line configured to transmit data and complementary data. Each transmission path has an amplifier circuit of each signal and a level adjustment circuit for reducing amplitude of output from the amplifier circuit. |
申请公布号 |
US8933739(B1) |
申请公布日期 |
2015.01.13 |
申请号 |
US201314021493 |
申请日期 |
2013.09.09 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Kouchi Toshiyuki;Yoshihara Masahiro |
分类号 |
H03K3/00;H03K3/012 |
主分类号 |
H03K3/00 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A semiconductor integrated circuit comprising:
a first clock signal transmission line configured to transmit a clock signal; a second clock signal transmission line configured to transmit a complementary clock signal of the clock signal; a clock amplifier circuit configured to output the clock signal and the complementary clock signal after amplifying signal levels thereof; a clock level adjustment circuit configured to supply the clock signal and the complementary clock signal to succeeding clock signal transmission lines after reducing amplitudes thereof amplified in the clock amplifier circuit; a first data transmission line configured to transmit data; a second data transmission line configured to transmit complementary data of the data; a data amplifier circuit configured to amplify and output the data and the complementary data; and a data level adjustment circuit configured to supply the data and the complementary data to succeeding data transmission lines after reducing amplitudes thereof amplified in the data amplifier circuit. |
地址 |
Minato-ku JP |