| 发明名称 |
METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING |
| 摘要 |
A method for fan-out wafer level chip packaging includes: providing a carrier substrate; forming a plurality of conductive base layers on a surface of the carrier substrate; mounting a plurality of chips on the conductive base layers and electrically connecting the chips to the conductive base layers by using a plurality of wire leads; forming a packaging layer to encapsulate the chips, the wire leads, the conductive base layers, and a top surface of the carrier substrate; removing the carrier substrate; and forming a plurality of conductive layers on bottom surfaces of the conductive base layers. |
| 申请公布号 |
US2016189983(A1) |
申请公布日期 |
2016.06.30 |
| 申请号 |
US201514975894 |
申请日期 |
2015.12.21 |
| 申请人 |
NANTONG FUJITSU MICROELECTRONICS CO., LTD. |
发明人 |
Shi Lei |
| 分类号 |
H01L21/56;H01L23/00;H01L23/498;H01L23/31 |
主分类号 |
H01L21/56 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for fan-out wafer level chip packaging, comprising:
providing a carrier substrate; forming a plurality of conductive base layers on a surface of the carrier substrate; mounting a plurality of chips on the conductive base layers and electrically connecting the chips to the conductive base layers by using a plurality of wire leads; forming a packaging layer to encapsulate the chips, the wire leads, the conductive base layers, and a top surface of the carrier substrate; removing the carrier substrate; and forming a plurality of conductive layers on bottom surfaces of the conductive base layers. |
| 地址 |
NANTONG CN |
