| 摘要 |
A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active command. The bit line over driving control signal generator for use in a semiconductor memory device includes a delaying unit for delaying an over driving signal generated in response to an active command to thereby output a delayed over driving signal, a controlling unit for determining whether the delayed over driving signal is outputted without any modification or outputted with being disabled in response to the over driving signal, a read command, and a precharge command, and a pulse width adding unit for adding a predetermined pulse width of the delayed over driving signal to the over driving signal to thereby output a bit line over driving control signal.
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