| 摘要 |
The purpose of the present invention is to provide a nonvolatile semiconductor storage device, which applies a voltage from a first control line (DLO) to a sub-control line (W11) as a memory gate voltage via a switching transistor (26a), while blocking application of the voltage to a corresponding sub-control line (W12) via another switching transistor (26b). Thereby, a plurality of memory cells (M11, M12, M21, M22) are arranged in the same direction along the first control line (DLO) while the switching transistor (26b) can be used to reduce the number of memory cells (M21, M22) to which the memory gate voltage is applied in order to minimize disturb errors accordingly. The sub-control line (W11) to which the memory gate voltage is applied from the first control line (DLO) is used as a gate for memory transistors (F11, F12). By forming the sub-control line (W11) and the gate in a single wiring layer, and the size of the device is reduced compared to a device where the sub-control line (W11) and the gate are formed in separate wiring layers. |
