Automatic equalization system

摘要

A phase lock control circuit comprising: an analog-to-digital converter for periodically sampling an analog signal representative of digital information in response to a sampling clock signal, and for converting every sample of the analog signal into a corresponding digital sample to convert the analog signal into a corresponding digital signal; first means for detecting a phase error between the sampling clock signal and the analog signal in response to a maximum likelihood related to the analog signal and also in response to a correlation between samples of the digital signal generated by the analog-to-digital converter; and second means for controlling a frequency of the sampling clock signal in response to the phase error detected by the first means.