| 摘要 |
<p>A mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. In certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable for processing by the co-processor. In certain embodiments a designated portion of memory (e.g., UCB) is utilized, wherein a host processor may place information in such UCB and the co¬ processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executabl for processing by the co-processor. In certain embodiments, the co-processor comprises dynamically reconfigurable logic, enabling the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to load onto the co-processor</p> |
