| 摘要 |
Disclosed are a semiconductor integrated circuit device, and a design and manufacturing method of the device, in which various semiconductor integrated circuit devices can be effectively designed and manufactured at low cost using a master slice method. A fixed layer used in common between Wire-Bonding (WB) chips and Flip-Chip (FC) chips is previously designed. When it is determined whether to form a WB chip or a FC chip, a variable layer for the WB chip or for the FC chip is designed. Based on this design, the WB chip or FC chip including the fixed layer and the variable layer added thereto is formed. Since the WB chip and the FC chip are differentially formed by the variable layer, the designing and manufacturing man-hour can be concentrated on the variable layer. Thus, reduction in TAT and in cost can be realized in design and manufacture of the device.
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