发明名称 |
Power Switch with Source-Bias Mode for on-chip Powerdomain Supply Drooping |
摘要 |
This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module. |
申请公布号 |
US2016357211(A1) |
申请公布日期 |
2016.12.08 |
申请号 |
US201615236743 |
申请日期 |
2016.08.15 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Venkatasubramanian Ramakrishnan;Stelmach Shane;Purushotaman Soman;Gill Michael;Flores Jose Luis |
分类号 |
G05F3/02;H03K17/687 |
主分类号 |
G05F3/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
Dallas TX US |