| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent the erroneous reception or erroneous judgment of a fare by sharply reducing the number of path patterns for simulation thereby verifying all the path patterns. <P>SOLUTION: A processing logic verification device is provided with: a storage means (3) for storing node data (31) in which crossing stations where different routes are connected and latches for transfer/connection are defined as nodes and block data (32) in which nodes on the same line are defined as blocks; a test ticket generation means (1) for generating a path pattern by reading the node data and the block data from the storage means, and for generating a test ticket; and a plurality of simulators (2-1 to 2-n) where the processing modules of station task equipment are assembled. Then, each simulator is made to read the test ticket, and to execute the processing of the station task equipment, and to compare the processing results of each simulator. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
