SEMICONDUCTOR CHIP

摘要

According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

主权项

1. A logic gate for implementing a logical function comprising:
a first circuit comprising
at least one p channel field effect transistor;at least one n channel field effect transistor;a first power supply terminal configured to receive a first supply voltage with an upper supply potential; anda second power supply terminal configured to receive a second supply voltage with a lower supply potential;wherein the at least one p channel field effect transistor and the at least one n channel field effect transistor are connected such that
the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; andthe at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor;wherein the circuit is configured such that the logic state of the gate of the at least one p channel field effect transistor and the logic state of the gate of the at least one n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and a second circuit implementing a logical function of the logic gate and having a supply terminal coupled to the gate of the at least one p channel field effect transistor or the gate of the at least one n channel field effect transistor.