PROCEDE POUR CONTRAINDRE UN MOTIF MINCE ET PROCEDE DE FABRICATION DE TRANSISTOR INTEGRANT LEDIT PROCEDE

摘要

The method involves etching at a periphery of a surface having dimensions greater than that of a pattern surface, of a buried layer of silicon oxide (3) and of a stress layer of silicon-germanium alloy (2) over a part of the depth of the layer of alloy, where the buried layer of silicon oxide is situated between a semiconductive material layer i.e. silicon layer (4), and the stress layer of silicon-germanium alloy. A function related to the trend of optimum thickness of the layer of alloy is determined as a function of a pattern dimension to obtain maximum stress in the pattern. An independent claim is also included for a method for manufacturing a transistor.