TECHNIQUES FOR IMPROVING ISSUE OF INSTRUCTIONS WITH VARIABLE LATENCIES IN A MICROPROCESSOR

摘要

Techniques are disclosed for issuing instructions in a processor. According to one embodiment of the present disclosure, an instruction tag is broadcast to wake up a plurality of instructions stored in an issue queue that are dependent on an issued instruction associated with the instruction tag. Each of the plurality of instructions has an execution latency. One or more of the instructions having an execution that will collide with an execution of one of the issued instructions if issued in a next clock cycle are identified based on the execution latencies. The identified one or more instructions are delayed from issue by at least one clock cycle after the next clock cycle.

主权项

1. A method for issuing instructions in a processor, comprising:
waking up a plurality of instructions stored in an issue queue that are dependent on an issued instruction of one or more issued instructions, each of the plurality of instructions having an execution latency; identifying, based on the execution latency of each of the plurality of instructions, one or more of the plurality of instructions having an execution that will collide with an execution of one of the issued instructions if issued in a next clock cycle; and delaying the identified one or more instructions from issue by at least one clock cycle after the next clock cycle.