发明名称 |
PATTERNING OF DOPED POLY-SILICON GATES |
摘要 |
A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.
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申请公布号 |
US2008096372(A1) |
申请公布日期 |
2008.04.24 |
申请号 |
US20070876617 |
申请日期 |
2007.10.22 |
申请人 |
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) |
发明人 |
DEMAND MARC;SHAMIRYAN DENIS;PARASCHIV VASILE |
分类号 |
H01L21/3205 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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