| 摘要 |
A robust phase-lock detector for a phase-locked loop examines both the sum frequency and baseband components of an error signal from the phase-locked loop to determine that both a reference signal and an output signal for the phase-locked loop are present and that the reference and output signals have a desired phase relationship. An IF detector selects the sum frequency component, which is the sum of the reference frequency and a subdivided frequency from the output signal, and detects its presence. A baseband detector selects the baseband component and detects whether the baseband component is approximately zero volts. The outputs from the IF detector and the baseband detector are combined to produce a lock signal, indicating that the phase-locked loop is locked, i.e., the reference and output signals are present and have the desired phase relationship with respect to each other.
|
