| 发明名称 |
REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY |
| 摘要 |
A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect transistor (nFET), the nFET including a high-k dielectric layer on an interlayer. The CMOS circuit also includes a p-channel field effect transistor (pFET), the pFET including the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal. Metal atoms from the cap layer do not intermix with the interlayer. |
| 申请公布号 |
US2016197073(A1) |
申请公布日期 |
2016.07.07 |
| 申请号 |
US201615068940 |
申请日期 |
2016.03.14 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Ando Takashi;Linder Barry P. |
| 分类号 |
H01L27/092;H01L29/49;H01L27/02;H01L29/51 |
主分类号 |
H01L27/092 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:
an n-channel field effect transistor (nFET), the nFET comprising a high-k dielectric layer on an interlayer; and a p-channel field effect transistor (pFET), the pFET comprising the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal, wherein metal atoms from the cap layer do not intermix with the interlayer. |
| 地址 |
Armonk NY US |
