| 摘要 |
PROBLEM TO BE SOLVED: To provide storage device capable of reducing a charge trap of a non-volatile memory cell while suppressing an increase in chip area and in load capacity, and the like.SOLUTION: A storage device includes: non-volatile memory cells M11, M12 and so on capable of electrically writing and erasing data; and a transistor TN. Word lines WS1 of the MONOS type non-volatile memory cells M11, M12 and so on and a gate electrode GT of the transistor TN are formed of common conductive wiring PL. A contact CNA for supplying a voltage to the word lines WS1 and the gate electrode GT is formed in the conductive wiring PL. In a plan view, a channel region of the transistor TN is formed in a route of the conductive wiring PL among the contact CNA and the non-volatile memory cells M11, M12 and so on. When a length of the channel region of the transistor TN is represented by D1, and a distance from an end portion of a contact side of the channel region to the contact CNA is represented by D2, DI and D2 satisfy D2<D1.SELECTED DRAWING: Figure 6 |
