发明名称 |
Contact resistance reduction employing germanium overlayer pre-contact metalization |
摘要 |
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired. |
申请公布号 |
US9484432(B2) |
申请公布日期 |
2016.11.01 |
申请号 |
US201514673143 |
申请日期 |
2015.03.30 |
申请人 |
INTEL CORPORATION |
发明人 |
Glass Glenn A.;Murthy Anand S.;Ghani Tahir |
分类号 |
H01L29/36;H01L29/66;H01L29/78;H01L29/08;H01L29/165 |
主分类号 |
H01L29/36 |
代理机构 |
Finch & Maloney PLLC |
代理人 |
Finch & Maloney PLLC |
主权项 |
1. A transistor device, comprising:
a substrate having a channel region; source and drain regions in the substrate and adjacent to the channel region; a boron doped germanium layer on at least a portion of the source and drain regions, the boron doped germanium layer comprising a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm−3; and a metal-germanide contact on the boron doped germanium layer. |
地址 |
Santa Clara CA US |