| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology which improves precision in circuit simulation in designing a semiconductor integrated circuit (IC) in which power MOS elements are mixedly mounted. SOLUTION: First, the gate parts of power MOS elements are virtually divided. When the MOS elements are virtually divided, diffusion-resistive elements for storing connection information are formed in the diffusion layer parts of the MOS elements. However, a trade-off relation exists, that is, precision in analysis is more improved as the respective MOS elements (segment 108) obtained as the result of the division becomes finer but time required for analysis (time required for simulation) increases. Accordingly, it is preferable to optionally set sizes of the division. Further, same as the gate parts, the wiring on the MOS elements is divided in optional sizes, and parasitic resistance is extracted for each wiring segment, and a mesh-shaped resistance net is formed. By this, more precise extraction of wiring parasitic resistance becomes possible. COPYRIGHT: (C)2008,JPO&INPIT
|
