TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM

摘要

An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

主权项

1. An electronic circuit comprising:
a pull-up transistor for pulling up an input/output (I/O) node to a first voltage; a first isolation transistor for coupling the pull-up transistor to the I/O node; a pull-down transistor for pulling down the I/O node to a second voltage; and a second isolation transistor for coupling the pull-down transistor to the I/O node, wherein the pull-up and the pull-down transistors comprise first metal-oxide-semiconductor transistor (MOSFET) devices supporting a first maximum drain-to-source voltage and a first maximum gate-to-source voltage, and wherein the first and the second isolation transistors comprise second MOSFET devices supporting the first maximum drain-to-source voltage and a second maximum gate-to-source voltage greater than the first maximum gate-to-source voltage.