| 摘要 |
1398438 Selecting alternative memory locations INTERNATIONAL BUSINESS MACHINES CORP 24 July 1972 [18 Aug 1971] 34452/72 Heading G4A A data store includes a memory array having several addressable lines of bit locations, a read only memory storing the address of a defective line, and a comparator having its output connected to an alternative line of bit locations provided in the memory array and arranged to compare an address supplied to the array with the address stored in the read only memory and, in the event of equality, to generate a pulse on its output to select the alternative line of bit locations. The memory is formed on a number of cards 12 each containing one or more integrated circuit chips, only one of which is shown. The memory 9 has nine word lines 31-39 and eight bit lines 21-28. The word lines 31-38 are normally selected by address decode circuits 40, the ninth line 39 being a spare. Following manufacture the memory is tested. If more than one word line contains a defective cell the memory is discarded. If no lines are defective the memory is used conventionally. If one word line contains a defective location its address is stored in read only memory 54 so that when subsequently the defective line is addressed comparator 52 generates an output on line 55 to disable the address decode circuits 40 and select the spare word line 39. More than one spare line may be provided with a read only memory and comparator for each spare line. In this way memories with more than one defective line may be used. Suitable circuits are described for the decoders 40, comparator 52, and read only memory 54. The read only memory consists of fusible links which are selectively blown to store the address of a defective word line, the comparator consists of transistor exclusive-OR gates, and the word line decoders consist of transistor NOR circuits. |
