| 摘要 |
<p>A lag control electrode (30) is mounted on that portion of a cell (10) constituting a picture element which is disposed on one end portion of an N+ layer (26). A gate electrode (32) is provided close to the other end portion of the N+ layer (26). Where a picture light (44) enters a solid state image sensor, then a signal charge (46) is generated in a P type semiconductor substrate (22). The signal charge (46) thus produced is collected in the N+ layer (26). Only during the period in which the lag control electrode (30) is impressed with a prescribed level of voltage, then part of the signal charge (46) is trapped in interface states between that portion of a Si02 layer (28) which lies belowthe lag control electrode (30) and the N+ layer (26). Only during the period in which the gate electrode (32) is impressed with a prescribed level of voltage, the signal charge collected in the N+ layer (26) is delivered to the channel layer (24) of a CCD shift register (14).</p> |
