| 摘要 |
A frequency generating circuit comprises a piezoelectric buzzer (18) which is driven by a driving signal having a desired frequency and a desired pulse width; a frequency dividing circuit (1) made up of a multi-stage flip-flop array for frequency dividing a reference frequency signal; logic setting means (31 to 36, 4) which is responsive to a plurality of externally generated setting signals (C1 to C6) to effect a logic setting for obtaining the desired frequency; control means (5, 6, 7, 10, 11, 12) for outputting a control signal to reset terminals of the flip-flops on the basis of an output signal of the logic setting means for resetting the frequency dividing circuit to obtain the desired frequency; pulse width setting means (15) coupled to output terminals of at least two predetermined flip-flop stages of the frequency dividing circuit to set the pulse width of a driving signal to the desired pulse width; and driving signal generating means (8, 13, 14, 16) for delivering a driving signal to the piezoelectric buzzer (18) as a function of the control signal of the control means and the output signal of the pulse width setting means, the driving signal having the desired frequency and the desired pulse width.
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