发明名称 REDIALING CONTROL SYSTEM
摘要 PURPOSE:To attain surely the management of number of digits of a dial number, by outputting a key input inhibiting flag during the operation for preventing malfunction due to key input. CONSTITUTION:An address counter 24 counts up a pulse of a prescribed period at each key input or with a redialing signal. An address decoder 25 decodes the content of the counter 24 and outputs an address signal ADR of a memory. A digital memory and a coincidence detecting circuit 26 store the content of the counter 24 and compares the content of the counter 24 with the redialing signal input with the storage content. Flip-flops 21, 22 are reset with a redialing signal RD and output respectively a key input inhibiting flag F1 during the redialing and a redialing key input inhibiting flag F2 after the operation. When the decoder 25 decodes the content of the counter 24 of >= the 2nd digit, the FF21 is reset by a coincidence signal out of the circuit 26. An RST is a reset signal by off-hooking.
申请公布号 JPS5916452(A) 申请公布日期 1984.01.27
申请号 JP19820125970 申请日期 1982.07.20
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA;NIPPON DENKI KK 发明人 FUKAZAWA HIDEO;SANO YOSHIO;NISHINO YUTAKA;MINAFUJI MASAYUKI;NISHIHARA KANEYUKI;HARA MICHIO
分类号 H04M1/27;H04M1/272;(IPC1-7):04M1/272 主分类号 H04M1/27
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