发明名称 MANUFACTURE OF FET
摘要 PURPOSE:To contrive the reduction in ON resistance by a method wherein an impurity is diffused to an Si substrate in the drain electrode side and a drain electrode is then formed on the surface thereof. CONSTITUTION:A P type Si layer 2 and an N type Si layer 3 are formed on the N type Si substrate 1, and an Si oxide film 4 is formed on the layer 3. Next, a V-groove reaching the substrate 1 is formed by opening the film 4. Then, the oxide film 4 is grown in the V-groove part, and successively each polycrystalline film 5 is grown. At this time, the films 4 and 5 grow also on the surface opposite to the V-groove. The films 4 and 5 on the back of the substrate are removed. Phosphorus is introduced to the film 5 and the back of the substrate 1 as the impurity. Thereby, a polycrystalline Si film 6 having a seat resistance of several OMEGA and an N type diffused layer 9 of high concentration are formed. The film 6 in the part other than the V-groove is removed, and the film 4 is opened at the source terminal lead-out part. Source electrodes 7 are formed and the drain electrode 8 is formed on the layer 9, and a gate N-channel MOSFET is formed by the V-groove shape S. This manner enables the reduction in ON resistance because of easy formation of the ohmic contact of the electrode 8.
申请公布号 JPS60182774(A) 申请公布日期 1985.09.18
申请号 JP19840039253 申请日期 1984.02.29
申请人 MATSUSHITA DENSHI KOGYO KK 发明人 NAGASAKI HIRONORI;SHIMANO AKIO;TAKAGI HIROMITSU
分类号 H01L29/41;H01L29/417;H01L29/78 主分类号 H01L29/41
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