| 摘要 |
PURPOSE:To attain high-speed sampling, to improve the processing capability of an MPU and to fetch efficiently process information by allowing a microprocessor (MPU) to readomly process information having state change after the process information fetched from each process input device once to an FIFO memory via a word serial bit parallel converter. CONSTITUTION:The work serial bit parallel (WSBP) converter 7 updates a clock signal (d) from a control circuit 9 normally in a speed of mus at first and it is outputted to n sets of PI/O via buffer 13 by an address counter 10. The data from the n sets of PI/O is given to a RAM11 and a state change detection circuit 12 and also to the FIFO memory 17. When the state change detection circuit 12 detects dissidence, a state change signal (g) is outputted to the control circuit 9 and the control circuit 9 receiving it outputs a strobe signal (a). When the state change detection circuit 12 detects the coincidence between old data U and new data, no strobe signal (a) is outputted.
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