| 摘要 |
PURPOSE:To suppress the current of a signal input section to a permissible value and to improve the power voltage characteristic of the oscillation frequency by setting the value of each gate capacitance of p-and n-channel MOSFETs in a CMOS inverter of the 2nd stage smaller than each gate capacitance of the lst stage inverter by a prescribed value only. CONSTITUTION:The dimension W/L of the p-and n-channel MOSFETs 1,2 in the lst stage inverter I1 is selected larger in a range where its input current is permitted. Further, the dimension W/L of the p-and n-channel MOSFETs 3,4 of the 2nd stage inverter I2 is selected smaller than that of the lst stage by a prescribed value only. Thus, the gate capacitance 11b of the inverter I2 of the 2nd stage being the output load capacitance of the lst stage inverter I1 is decreased. In selecting the W/L of the p-and n-channel MOSFETs 3,4 constituting the 2nd stage inverter I2 smaller than that of the lst stage in this way, the capacitance C1 of the gate capacitance 11b of the 2nd stage inverter I2 is lowered and the increasing tendency of the propagation delay time T is compensated.
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