| 摘要 |
PURPOSE:To decrease number of components of a frequency division circuit possibly by constituting a part corresponding to a holding circuit by a biphase dynamic shift register, connecting plural stages of dynamic shift registers in a form of feedback and applying biphase oscillation to apply frequency division in the clock synchronism. CONSTITUTION:As a frequency division output COUT1 of a 1st stage frequency division circuit FF1, the period of clocks CP1, CP2 is outputted through 1/2 frequency division. Moreover, the frequency division output COUT1 of the FF1 is being frequency-divided by 1/2 each by frequency division circuits FF2, FF3 on the 2nd and succeeding stages. The holding circuit constituting the frequency divider circuit 10 of each stage is constituted by the biphase dynamic shift register in the multi-stage frequency divider circuit 10 and in addition, odd number stages of the biphase dynamic shift registers are connected in a form of feedback and frequency division is applied through biphase oscillation at the clock synchronism. Thus, the circuit inputting the frequency division input or extracting the frequency division output is constituted by having only to use one AND gate G12.
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