| 摘要 |
PURPOSE:To constitute an asynchronous system bus with high reliability and efficiency and to reduce load on design, by outputting a control signal delayed by a delay means as a signal to be selected. CONSTITUTION:An address signal AD from the outside is inputted to a decoder DEC, and one memory cell MC in a memory cell array is selected by an outputted selection signal SEL. One side of complementary data line pairs D and the inverse of D is set at an H and the other side at an L corresponding to the bit of storage information of the MC. A level difference is amplified by a differential sense amplifier SA, and a readout data Dout is outputted to the outside through a latch circuit LT and an output buffer DOB. A chip select signal CS is delayed by a delay circuit DLY1 or a DLY2 having a delay time equivalent to an access time from the input of a signal AD to the output of the sense amplifier SA or the buffer DOB, or a write time on the memory MC, then, a buffer ODB or an acknowledge signal DTACK is outputted.
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