| 摘要 |
PURPOSE:To smoothly process the compression of an image in a horizontal direction without performing the correction of picture element data, by providing a two phase clock generation circuit which generates a two phase clock and a switching circuit which switches the two phase clock with a prescribed timing. CONSTITUTION:In the two phase clock generation circuit 7, the two phase clock is generated from an input clock, and is inputted to the switching circuits 14 and 15 via counters 5 and 6, decoders 3, 4 and 8, latches 11 and 12, and an FF13, respectively. Next, out of the two phase clocks generated at the circuit 7, first clock is outputted generally, and the clock and the next clock are switched to second clock at every (N+1)-th of the first clock. And the clock with the N/(N+1) times the number of the clocks of the first clock are generated, and they are set as the clocks for A/D conversion and write clocks on a memory. In such a way, it is possible to write an input image in the horizontal direction on the memory 17 by compressing to the N/(N+1) times, and to perform a compression processing fitting to the compression mode of 1/(N+l) times.
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