| 摘要 |
The circuit for minimizing the execution load of the CPU during the attribute mode comprises a memory unit (10) for video data memory, the first latch unit (20) which assigns the attributes, the second latch unit (30) for the low control word latch, a selection unit (40) for hidden or display mode selection, the third latch unit (50) for output data latch, and the forth latch unit (60).
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