SEMICONDUCTOR MEMORY DEVICE

摘要

The semiconductor memory device having a low power data retention function includes a refresh enable circuit for generating a self-refresh enable signal responsive to a prescribed period of a self-refresh clock, a backbias control clock generating circuit for receiving the self-refresh clock and internal addresses and generating a backbias control clock which is one of input signals, a select circuit for supplying a signal responsive to the self-refresh enable signal and the backbias control clock to an oscillator, and a program circuit for generating a control signal so as to generate any one of the input signals of the backbias control clock generating circuit as the backbias control clock, thereby reducing power dissipated in data retention.