发明名称 FLATTENING METHOD AND FLATTENED ELEMENT
摘要 <p>PURPOSE:To provide a glass substrate wherein a gate resistance is small and no difference in level exists. CONSTITUTION:When an insulating film 106 is etched by making use of a resist 107 as a mask, a gate pattern and the insulating film are flattened on nearly the same face. Although there may be a case in which a gap is produced at the end of a gate, the gap can be filled in self-aligned manner with an anodic oxidation film when aluminum is anodized. When an ITO is applied in advance, SiNx at the part of the ITO can be removed when light for the exposure of the resist is selected at a wavelength absorbed by the ITO and an effect which is equal to a pixel opening can be obtained.</p>
申请公布号 JPH06326130(A) 申请公布日期 1994.11.25
申请号 JP19930114456 申请日期 1993.05.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIHARA SHINICHIRO
分类号 G02F1/136;G02F1/1368;H01L21/302;H01L21/3065;H01L21/3205;H01L21/336;H01L29/78;H01L29/786;(IPC1-7):H01L21/336;H01L29/784;H01L21/320 主分类号 G02F1/136
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