| 摘要 |
<p>PURPOSE: To provide a synchronous memory in which a data, corresponding to an inputted address, is delivered from the core part within same clock cycle while enhancing the cycle time. CONSTITUTION: A timing generator 14 generates a clock signal E where the time interval of 'L' level is longer than that of 'H' level. Address and control signal are latched at the rising time of the clock signal E and a data corresponding to the address of a synchronous memory 10 is read out at the falling time of the clock signal E.</p> |
