发明名称 MESSAGE RECEPTION CONTROL SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To set memory management overhead to be a minimum and to effectively use a memory. SOLUTION: In parallel processors, plural nodes ND0 -NDn constituted by instruction processors IP0 -IPn and main storages MS0 -MSn are connected by a network. In the respective nodes ND0 -NDn , processes are executed under the control of an operating system, and the nodes ND0 -NDn execute inter-process communication through the network so as to receive messages. Reception buffers reside in the main storages MS0 -MSn and they are constituted by pool pages which are not continuous in terms of logical address or real address on a virtual space which the processes executed in the nodes ND0 -NDn use. Reception buffer control information is arranged on the main storages MS0 -MSn and they manage the reception buffers. The nodes ND0 -NDn receiving the messages obtain the real addresses on reception buffer pools receiving the messages by using communication control information included in the received messages and reception buffer control information.</p>
申请公布号 JPH09167143(A) 申请公布日期 1997.06.24
申请号 JP19950327264 申请日期 1995.12.15
申请人 HITACHI LTD 发明人 KOSUGI HIDENORI;PATORITSUKU HAMIRUTON
分类号 G06F15/17;G06F13/00;G06F15/16;G06F15/177;(IPC1-7):G06F15/16 主分类号 G06F15/17
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