发明名称 METHOD AND SYSTEM REDUCING POWER CONSUMPTION IN ELECTRONIC CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To make an electronic circuit consume small electric power by loading up to a specific number of data bits from a memory in every cycle of a load circuit while the load circuit operates in 1st or 2nd electric power mode. SOLUTION: When the load circuit of a processor operates in full electric power mode as the 1st electric power mode, a fetch logic circuit 71 requests up to two data bits selectively from an instruction cache 14 and stores and loads those data bits to an instruction buffer 70. Further, when the load circuit operates in low electric power mode as the 2nd electric power mode, the fetch logic circuit 71 requests up to up to one data bit in every cycle of the load circuit of the processor and loads the one data bit to the instruction buffer 70. Consequently, the power consumption in the electronic circuit is reducible.</p>
申请公布号 JPH10124203(A) 申请公布日期 1998.05.15
申请号 JP19970265795 申请日期 1997.09.30
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 ALBERT J LAUPER;SUUMUYA MARRIC
分类号 G06F1/26;G06F1/32;G06F9/312;G06F9/38;G06F12/08;(IPC1-7):G06F1/32 主分类号 G06F1/26
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